An analog signal high speed acquisition system using a tapped delay line to generate track-and-hold signals is known from U.S. Pat. No. 5,144,525 (Saxe, et al.) issued Sep. 1, 1992. The tapped delay line was realized as a cascade of buffer amplifiers each of which produced a delayed versions of a clock signal. That system recognized that excessive or insufficient buffer delay could cause improper operation, and provided a feedback circuit to ensure that the total delay of the tapped delay line was exactly equal to one clock cycle.
The above-mentioned '525 patent shows that the feedback (i.e., delay correction) signal is applied to a phase shifting circuit to shift one edge of each of the clock signals to a position in accordance with its proper timing relationship to the next signal of the delay line.
One embodiment of the teaching of the '525 patent is known from the TDS-500 series of oscilloscopes, manufactured by Tektronix, Inc. Wilsonville, Oreg. While that embodiment worked quite well, one limitation was encountered. Specifically, two delay lines and corresponding sampling cells were required, because following an active mode, the delay line chain requires a precharge interval before it can be utilized again. Thus, two delay lines operating in complementary timing were required to cover the acquisition period without "holes" due to precharge intervals. What is needed is a less complex system, dissipating a lower level of power, and requiring relatively less chip area.